Nvidia snaps up AI chip packaging capacity as TSMC expands in U.S.

An underappreciated step in the chip-making process is poised to become the next bottleneck for artificial intelligence.

Every microchip used to power artificial intelligence must be built into hardware that can interact with the outside world. But right now, this chipmaking step, known as advanced packaging, takes place almost entirely in Asia, and capacity is in short supply.

Now taking center stage Taiwan Semiconductor Manufacturing Inc. Preparing to break ground on two new facilities and Elon Musk taps in Arizona Intel for ambitious custom chip plans.

“If people don’t proactively make capital spending investments to account for the increase in factory production over the next few years, this could very quickly emerge as a bottleneck,” said John VerWey of Georgetown University’s Center for Security and Emerging Technology.

In a rare interview, Paul Rousseau, president of packaging solutions for TSMC North America, told CNBC that the numbers have “increased very significantly.”

Its most advanced method currently in use is called Chip on Wafer on Substrate, or CoWoS, and Rousseau said it is growing at a staggering compound annual growth rate of 80%.

artificial intelligence giant Nvidia It has allocated the majority of the state-of-the-art capacity available at TSMC, the volume leader in packaging.

However, Intel is technologically at the same level as the Taiwanese giant.

The US chipmaker has tried to secure a major foreign customer for its chip manufacturing business, but its packaging customers include: Amazon And Cisco.

On Tuesday, Musk also talked about SpaceX, xAI and Tesla’s At the ambitious Terafab factory it is planning for Texas.

Intel does most of the final packaging in Vietnam, Malaysia and China. Some of Intel’s most advanced packaging is done at U.S. facilities in New Mexico, Oregon and a facility in Chandler, Arizona, where CNBC toured in November.

The process has attracted attention as AI challenges the density, performance and efficiency needs of chip makers racing to make the best hardware for inference workloads. As transistor density approaches physical limits, new silicon packaging methods could help.

“This is actually a natural extension of Moore’s Law into the third dimension,” Rousseau said.

For decades, individual chips, known as dies, have been removed from a single wafer and packaged into a system that connects to devices such as computers, robots, cars and cell phones. More advanced packaging methods have emerged as chip complexity has exploded over the past few years with the advent of artificial intelligence.

Now multiple dies, such as logic chips and high-bandwidth memory, are packaged into a larger chip, such as a graphics processing unit or GPU. Advanced packaging is used to connect all these molds and allow them to communicate with each other and the wider system.

“Until about 5 or 6 years ago, no one was doing this,” said chip analyst Patrick Moorhead of Moor Insights & Strategy, adding that packaging was an “afterthought” that companies assigned to junior engineers.

“We now know frankly that this is as important as the membrane itself,” he said.

Bottleneck

Nvidia has majority reserved Leveraging TSMC’s leading CoWoS technology, the capacity is so dense that TSMC reportedly It outsourced some steps to third-party companies such as ASE and Amkor, which specialize in simpler parts of the process.

ASE, the world’s largest outsourced semiconductor assembly and testing company, makes progress in packaging sales It will double in 2026. ASE is building a major new facility in Taiwan; where subsidiary SPIL held a grand opening for another new packaging facility last year, attended by Nvidia CEO Jensen Huang.

TSMC is also expanding two new packaging facilities in Taiwan, as well as building two packaging facilities in Arizona.

Currently, TSMC ships 100% of its chips to Taiwan for packaging, including chips produced at its advanced chip manufacturing facility in Phoenix, Arizona. TSMC has not announced a timeline for completion of its U.S. packaging facilities.

“Having this capability right next to the factory in Arizona will make their customers very happy,” Jan Vardaman, lead packaging researcher at TechSearch International, told CNBC.

This, he added, is because it will shorten turnaround time by eliminating the need to ship items back and forth between Asia and the United States.

Intel is currently doing some packaging near its new advanced 18A chip manufacturing facility in Arizona.

The US chipmaker has yet to find a major external customer for chip production at its 18A factory, but head of foundry services Mark Gardner told CNBC that the company has had customers for packaging since 2022, including Amazon and Cisco.

Nvidia is also considering bagging Intel as part of its $5 billion investment in the chip maker, weeks after the U.S. government invested $8.9 billion in 2025.

“Chip companies want to show the US government that they will do business with Intel and that the lower-risk way to do business with Intel is to do packaging,” Moorhead said.

Asked whether Intel could find a major chipmaker customer by going through the back door of advanced packaging, Gardner said there is “a path to that” for some customers.

“There are benefits to having everything in one place,” he said.

Musk may have been an early adopter at Intel in both chipmaking and packaging.

One Intel LinkedIn post It was said on Tuesday that the company’s “ability to design, manufacture and package ultra-high-performance chips at scale” will help Musk’s Terafab reach its goal of producing 1 terawatt of computing annually to power artificial intelligence.

Switching from 2D to 3D

Many chips, such as central processing units, are made with 2D packaging. More complex chips like GPUs need something extra; This is the field of CoWoS, TSMC’s 2.5D packaging format.

For these chips, an additional layer of high-density wiring, called an interposer, adds tighter interconnects, allowing high-bandwidth memory to be mounted directly around the chip, effectively eliminating what is often called the memory wall.

“You can’t get enough memory inside your compute chip to fully utilize it. So when we introduce CoWoS, we can bring HBM memory right next to the compute in a very efficient way,” said TSMC’s Rousseau.

TSMC pioneered the 2.5D technique in 2012 and has gone through many innovations since then. TSMC said Nvidia’s Blackwell GPUs are the first products built with the latest generation of CoWoS-L.

It’s this last capacity that has everyone worried, as Nvidia has reportedly reserved majority.

Intel’s leading packaging technology is called embedded multi-die interconnect bridge, or EMIB. It works similar to the process used by Taiwan Semi, but uses silicone bridges instead of intermediate elements.

“We get a cost advantage by placing these really small pieces of silicon right where they’re needed,” Intel’s Gardner said.

All players are also working on the next step, 3D packaging.

Intel calls its method Foveros Direct, while TSMC calls it System on Integrated Chips, or SoIC.

“Instead of putting the chips side by side, we now put them on top of each other,” Rousseau explained, “so they can actually act as one chip, and that gives a whole other performance boost.”

Rousseau said it will be a few years before we see TSMC packaging products with SoIC.

Meanwhile, Samsung, SK Hynix and Micron They have their own advanced packaging factory where they use 3D packaging to stack molds into high bandwidth memory.

As memory and logic chip makers scramble to get chips out the door, they are looking to replace bumps with copper pads with a new method called hybrid bonding, increasing the number of chips that can fit in a stack.

“Instead of a hump, we can do a pad-to-pad connection with almost no distance, which gives us better power performance,” Vardaman explained. “It also gives us better electrical performance because the shortest path is the best path.”

Watch: How advanced packaging is improving AI chips in the third dimension